//==========================================================================
// Copyright (c) 2000-2008,  Elastos, Inc.  All Rights Reserved.
//==========================================================================

#ifndef __ELASTOS_TIMER_H__
#define __ELASTOS_TIMER_H__

enum {
    PIT_ClockRate               = 512000,                       // unit: HZ
    PIT_ClockCycle              = (1000000000 / PIT_ClockRate), // unit: NS
};

enum {
    PIT_Irq                     = 9,
};

// Registers' IO address
#define _SYSCON1    ((ioport_t)0x80000100)
#define _TC1D       ((ioport_t)0x80000300) // Timer Counter 1 Data Register
#define _TC2D       ((ioport_t)0x80000340) // Timer Counter 2 Data Register

// SYSCON1 The System Control Register 1
#define _TC1M   __32BIT(4)  // Timer counter 1 mode. Setting this bit sets TC1
                            //  to prescale mode, clearing it sets free
                            //  running mode.
#define _TC1S   __32BIT(5)  // Timer counter 1 clock source. Setting this bit
                            //  sets the TC1 clock source to 512 kHz, clearing
                            //  it sets the clock source to 2 kHz.
#define _TC2M   __32BIT(6)  // Timer counter 2 mode. Setting this bit sets TC2
                            //  to prescale mode, clearing it sets free
                            //  running mode.
#define _TC2S   __32BIT(7)  // Timer counter 2 clock source. Setting this bit
                            //  sets the TC2 clock source to 512 kHz, clearing
                            //  it sets the clock source to 2 kHz.

#endif // __ELASTOS_TIMER_H__
